Chip multi-processors (CMPs) are now the dominant form of commercially available processor design. A CMP is a single chip on which are integrated multiple processor cores. The number and type of these cores on any given chip is generally limited by the die area. Processor architects have worked to develop efficient combinations of cores to integrate onto a single chip: for example, a single chip may be designed to include numerous small, simple cores, or it may be designed to accommodate a few larger, sophisticated cores. The design that is chosen can affect the processor's ability to handle threads of execution (threads), which are portions of a computer program that can run independently of and concurrently with other portions of the program. Typically, a chip with numerous small cores better accommodates computing environments characterized by higher thread parallelism, while a chip with fewer large cores is used in environments characterized by higher individual thread complexity.
A development in chip architecture is the Heterogeneous CMP. A Heterogeneous CMP is a die area on which are integrated some combination of both small, simple cores, and larger, more sophisticated cores. Thus, the cores on a Heterogeneous CMP may differ in their instruction sets; they may have various accelerators, such as Digital Signal Processing (DSP) or Streaming SIMD (SSE) extensions; their caches may vary in size; or they may have other complex design characteristics, such as branch predictors. This heterogeneous design results from many complex computing environments utilizing both high thread parallelism and high thread complexity where the requirements of distinct threads differ and individual thread may differ in its processor resource requirements over time.